FPGA Implementation of Channel Mismatch Calibration in TIADCs for Signals in Any Nyquist Bands

Han Le Duc, Van-Phuc Hoang, Duc-Minh Nguyen

Abstract


This paper presents a fully digital background calibration technique of the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converters for the wideband bandlimited input signal at any Nyquist bands. The proposed technique does not require an additional reference channel nor a pilot input. The channel mismatch parameters are estimated based on the mismatch frequency band. The experimental results shows the efficiency of the proposed mitigation technique with the SNDR improvement of 16dB for 4-channel 60dB SNR TIADC clocked at 2.7GHz given a multi-tone input occupied at the third Nyquist band. The hardware architecture of the proposed technique is designed and validated on Altera FPGA DE4 board. The synthesized design utilizes a very little amount of the hardware resource in the FPGA chip and works correctly on a Hardware-In-the-Loop emulation framework.

Full Text:

PDF

References


J. Black, W.C. and D. Hodges, “Time interleaved converter arrays,” Solid-State Circuits, IEEE Journal of, vol. 15, no. 6, pp. 1022–1029, Dec 1980.

B. Razavi, “Design Considerations for Interleaved ADCs,” Solid-State Circuits, IEEE Journal of, vol. 48, no. 8, pp. 1806–1817, 2013.

C. Vogel et al., “Adaptive blind compensation of gain and timing mismatches in M-channel time-interleaved ADCs,” in Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on, 2008, pp. 49–52.

——, “All-digital Calibration Techniques of Timing Skews for Undersampling Time-Interleaved ADCs,” Ph.D. dissertation, COMELEC Department, Telecom-ParisTech, 46 Rue Barrault, 75013 Paris, Dec 2015.

D. Stepanovic and B. Nikolic, “A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,” Solid-State Circuits, IEEE Journal of, vol. 48, no. 4, pp. 971–982, April 2013.

M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit timeinterleaved flash ADC with background timing skew calibration,” in VLSI Circuits (VLSIC), 2010 IEEE Symposium on, June 2010, pp. 157–158.

D. Camarero et al., “Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, no. 11, pp. 3676–3687, 2008.

N. Le Dortz et al., “22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, Feb 2014, pp. 386–388.

J. Matsuno et al., “All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 60, no. 5, pp. 1113–1121, 2013.

P. Satarzadeh et al., “A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, May 2010, pp. 4053–4056.

V. Divi and G. W. Wornell, “Blind Calibration of Timing Skew in TimeInterleaved Analog-to-Digital Converters,” Selected Topics in Signal Processing, IEEE Journal of, vol. 3, no. 3, pp. 509–522, 2009.

S. Huang and B. Levy, “Blind Calibration of Timing Offsets for FourChannel Time-Interleaved ADCs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 54, no. 4, pp. 863–876, April 2007.

T. Oshima et al., “Lms calibration of sampling timing for time interleaved a/d converters,” Electronics Letters, vol. 45, no. 12, pp. 615–617, June 2009.

J. A. McNeill et al., “’Split ADC’ Calibration for All-Digital Correction of Time-Interleaved ADC Errors,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 344–348, May 2009.

S. Jamal et al., “Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 52, no. 4, pp. 822–822, 2005.

F. Centurelli et al., “Efficient Digital Background Calibration of Time Interleaved Pipeline Analog-to-Digital Converters,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, no. 7, pp. 1373–1383, 2012.

F. Harris et al., “Two channel TI-ADC for communication signals,” in 2011 IEEE 12th International Workshop on Signal Processing Advances in Wireless Communications, June 2011, pp. 576–580.

——, “All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 1, pp. 99–103, Jan 2016.

——, “Fully digital feedforward background calibration of clock skews for sub-sampling tiadcs using the polyphase decomposition,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 6, pp. 1515–1528, June 2017.

S. Louwsma et al., “A Time-Interleaved Track & Hold in 0.13m CMOS sub-sampling a 4 GHz signal with 43 dB SNDR,” in Custom IntegratedCircuits Conference, 2007. CICC ’07. IEEE, Sept 2007, pp. 329–332.

C. Vogel, “The Impact of Combined Channel Mismatch Effects in Time-Interleaved ADCs,” IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 1, Feb. 2005.

J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principles, Algorithms and Applications. Upper Saddle River, New Jersey, 2007.

——, “Hardware implementation of all digital calibration for undersampling TIADCs,” Proc. 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, pp. 2181–2184.

P. Diniz, Adaptive Filtering: Algorithms and Practical Implementation, Kluwer international series in engineering and computer science, Springer, 2008.




DOI: http://dx.doi.org/10.21553/rev-jec.175

Copyright (c) 2018 REV Journal on Electronics and Communications

Copyright © 2011-2024
Radio and Electronics Association of Vietnam
All rights reserved