An Overview of H.264 Hardware Encoder Architectures Including Low-Power Features

Ngoc-Mai Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Edith Beigne, Suzanne Lesecq, Pascal Vivet, Xuan-Tu Tran

Abstract


H.264 is the most popular video coding standard with high potent coding performance. For its efficiency, the H.264 is expected to encode real-time and/or high-definition video. However, the H.264 standard also requires highly complex and long lasting computation. To overcome these difficulties, many efforts have been deployed to increase encoding speed. Besides, with the revolution of portable devices, multimedia chips for mobile environments are more and more developed. Thus, power-oriented design for H.264 video encoders is currently a tremendous challenge. This paper discusses these trends and presents an overview of the state of the art on power features for different H.264 hardware encoding architectures. We also propose the VENGME’s design, a particular hardware architecture of H.264 encoder that enables applying low-power techniques and developing power-aware ability. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at Register-Transfer-Level (RTL), is only 19.1 mW.


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DOI: http://dx.doi.org/10.21553/rev-jec.72

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